DSP56303 datasheet(246/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

B-2

Freescale Semiconductor

Programming Reference

B.1 Internal I/O Memory Map

HI08

Figure B-9, "Host Transmit Data Register"

page B-18

Figure B-10, "Host Base Address and Host Port Control Registers"

page B-19

Figure B-11, "Host Control Register"

page B-20

Figure B-12, "Interrupt Control and Command Vector Registers"

page B-21

Figure B-13, "Interrupt Vector and Host Transmit Data Registers"

page B-22

ESSI

Figure B-14, "ESSI Control Register A (CRA)"

page B-23

Figure B-15, "ESSI Control Register B (CRB)"

page B-24

Figure B-16, "ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)"

page B-25

SCI

Figure B-17, "SCI Control Register (SCR)"

page B-26

Figure B-18, "SCI Clock Control Registers (SCCR)"

page B-27

Timers

Figure B-19, "Timer Prescaler Load Register (TPLR)"

page B-28

Figure B-20, "Timer Control/Status Register (TCSR)"

page B-29

Figure B-21, "Timer Load, Compare, and Count Registers (TLR, TCPR, TCR)"

page B-30

GPIO

Figure B-22, "Host Data Direction and Host Data Registers (HDDR, HDR)"

page B-31

Figure B-23, "Port C Registers (PCRC, PRRC, PDRC)"

page B-32

Figure B-24, "Port D Registers (PCRD, PRRD, PDRD)"

page B-33

Figure B-25, "Port E Registers (PCRE, PRRE, PDRE)"

page B-34

Table B-2. Internal I/O Memory Map (X Data Memory)

Peripheral

16-Bit Address

24-Bit Address

IPR

$FFFF

$FFFFFF

Interrupt Priority Register Core (IPRC)

$FFFE

$FFFFFE

Interrupt Priority Register Peripheral (IPRP)

PLL

$FFFD

$FFFFFD

PLL Control Register (PCTL)

OnCE

$FFFC

$FFFFFC

OnCE GDB Register (OGDB)

BIU

$FFFB

$FFFFFB

Bus Control Register (BCR)

$FFFA

$FFFFFA

DRAM Control Register (DCR)

$FFF9

$FFFFF9

Address Attribute Register 0 (AAR0)

$FFF8

$FFFFF8

Address Attribute Register 1 (AAR1)

$FFF7

$FFFFF7

Address Attribute Register 2 (AAR2)

$FFF6

$FFFFF6

Address Attribute Register 3 (AAR3)

$FFF5

$FFFFF5

ID Register (IDR)

Table B-1. Guide to Programming Sheets (Continued)

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