DSP56303 datasheet(122/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

6-22

Freescale Semiconductor

Host Interface (HI08)

6.7.1 Interface Control Register (ICR)

The ICR is an 8-bit read/write control register by which the host processor controls the HI08

interrupts and flags. The DSP core cannot access the ICR. The ICR is a read/write register, which

allows the use of bit manipulation instructions on control register bits. Hardware and software

reset clear the ICR bits.

Table 6-14. Host-Side Register Map

Host Address

Big Endian HLEND = 0

Little Endian HLEND = 1

ICR

Interface Control

CVR

Command Vector

ISR

Interface Status

IVR

Interrupt Vector

00000000

Unused

5RXH/TXH

RXL/TXL

Receive/Transmit

Data

6RXM/TXM

RXM/TXM

RXL/TXL

RXH/TXH

765

432

INIT

HLEND

HF1

HF0

HDRQ TREQ RREQ

—Reserved bit; read as 0; write to 0 for future compatibility.

Figure 6-15. Interface Control Register (ICR)

Table 6-15. Interface Control Register (ICR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

7INIT0

Initialize

The host processor uses INIT to force initialization of the HI08 hardware.

During initialization, the HI08 transmit and receive control bits are configured.

Use of the INIT bit to initialize the HI08 hardware depends on the software

design of the interface. The type of initialization when the INIT bit is set

depends on the state of TREQ and RREQ The INIT command, which is local

to the HI08, configures the HI08 into the desired data transfer mode. When

the host sets the INIT bit, the HI08 hardware executes the INIT command.

The interface hardware clears the INIT bit after the command executes.

TREQ

RREQ

After INIT Execution

Transfer Direction

INIT = 0

None

INIT = 0;

RXDF = 0; HTDE = 1

DSP to host

INIT = 0;

TXDE = 1; HRDF = 0

Host to DSP

INIT = 0;

RXDF = 0; HTDE = 1;

TXDE = 1; HRDF = 0

Host to/from DSP

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