DSP56303 datasheet(118/292 Pages) FREESCALE

118 / 292 page

DSP56303 User’s Manual, Rev. 2

6-18

Freescale Semiconductor

Host Interface (HI08)

HAEN

Host Acknowledge Enable

Controls the HACK signal. In the single host request mode (HDRQ is cleared

in the ICR), if HAEN and HREN are both set, HACK/HRRQ is configured as

the host acknowledge (HACK) input. If HAEN or HREN is cleared,

HACK/HRRQ is configured as a GPIO signal according to the value of the

HDDR and HDR. In the double host request mode (HDRQ is set in the ICR),

HAEN is ignored.

HREN

Host Request Enable

Controls the host request signals. If HREN is set and the HI08 is in the single

host request mode (that is, if HDRQ is cleared in the host interface control

output. If HREN is cleared, HREQ/HTRQ and HACK/HRRQ are configured

as GPIO signals according to the value of the HDDR and HDR.

If HREN is set in the double host request mode (that is, if HDRQ is set in the

ICR), HREQ/HTRQ is configured as the host transmit request (HTRQ) output

and HACK/HRRQ as the host receive request (HRRQ) output. If HREN is

cleared, HREQ/HTRQ and HACK/HRRQ are configured as GPIO signals

according to the value of the HDDR and HDR.

HCSEN

Host Chip Select Enable

If the HCSEN bit is set, HCS/HA10 is a host chip select (HCS) in the

non-multiplexed bus mode (that is, when HMUX is cleared) and host address

line 10 (HA10) in the multiplexed bus mode (that is, when HMUX is set). If

this bit is cleared, HCS/HA10 is configured as a GPIO signal according to the

value of the HDDR and HDR.

HA9EN

Host Address Line 9 Enable

If HA9EN is set and the HI08 is in multiplexed bus mode, then HA9/HA2 is

host address line 9 (HA9). If this bit is cleared and the HI08 is in multiplexed

bus mode, then HA9/HA2 is configured as a GPIO signal according to the

value of the HDDR and HDR.

NOTE: HA9EN is ignored when the HI08 is not in the multiplexed bus mode

(that is, when HMUX is cleared).

HA8EN

Host Address Line 8 Enable

If HA8EN is set and the HI08 is in multiplexed bus mode, then HA8/A1 is

host address line 8 (HA8). If this bit is cleared and the HI08 is in multiplexed

bus mode, then HA8/HA1 is a GPIO signal according to the value of the

HDDR and HDR.

NOTE: HA8EN is ignored when the HI08 is not in the multiplexed bus mode

(that is, when HMUX is cleared).

0HGEN0

Host GPIO Port Enable

Enables/disables signals configured as GPIO. If this bit is cleared, signals

configured as GPIO are disconnected: outputs are high impedance, inputs

are electrically disconnected. Signals configured as HI08 are not affected by

the value of HGEN.

Table 6-12. Host Port Control Register (HPCR) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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