DSP56303 datasheet(116/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

6-16

Freescale Semiconductor

Host Interface (HI08)

6.6.6 Host Port Control Register (HPCR)

The HPCR is a read/write control register that controls the HI08 operating mode. HPCR bit

initialization values are discussed in Section 6.6.9, DSP-Side Registers After Reset, on page

6-20. Hardware and software reset clear the HPCR bits.

To assure proper operation of the DSP56303, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX,

HASP, HDSP, HROD, HAEN, and HREN should be changed only if HEN is cleared. Similarly,

the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN,

HCSEN, HA9EN, and HA8EN should not be set when HEN is set nor at the time HEN is set.

Figure 6-11. Self Chip-Select Logic

HAP

HRP HCSP HDDS HMUX HASP HDSP HROD

HEN HAEN HREN HCSEN HA9EN HA8EN HGEN

—Reserved bit, read as 0; write to 0 for future compatibility.

Figure 6-12. Host Port Control Register (HPCR) (X:$FFFFC4)

Table 6-12. Host Port Control Register (HPCR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

HAP

Host Acknowledge Polarity

If HAP is cleared, the host acknowledge (HACK) signal is configured as an

active low input. The HI08 drives the contents of the IVR onto the host bus

when the HACK signal is low. If the HAP bit is set, the HACK signal is

configured as an active high input. The HI08 outputs the contents of the IVR

when the HACK signal is high.

HRP

Host Request Polarity

Controls the polarity of the host request signals. In single host request mode

(that is, when HDRQ is cleared in the ICR), if HRP is cleared and host

requests are enabled (that is, if HREN is set and HEN is set), then the HREQ

signal is an active low output. If HRP is set and host requests are enabled,

the HREQ signal is an active high output. In the double host request mode

(that is, when HDRQ is set in the ICR), if HRP is cleared and host requests

are enabled (that is, if HREN is set and HEN is set), then the HTRQ and

HRRQ signals are active low outputs. If HRP is set and host requests are

enabled, the HTRQ and HRRQ signals are active high outputs.

HAD[0–7]

Chip select

A[3–7]

8 bits

HAS

HA[8–10]

DSP Peripheral

Data Bus

Latch

Base

Address

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