DSP56303 datasheet(112/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

6-12

Freescale Semiconductor

Host Interface (HI08)

addressing modes. In addition, the MOVEP instruction allows direct data transfers between

DSP56303 internal memory and the HI08 registers or vice versa.

There are two types of host processor registers, data and control, with eight registers in all. The

DSP core can access all eight registers, but the external host cannot. The following data registers

are 24-bit registers used for high-speed data transfers by the DSP core.

Host data receive register (HRX), on page 6-19

Host data transmit register (HTX), on page 6-19

The DSP-side control registers are 16-bit registers that control HI08 functionality:

Host control register (HCR), on page 6-12

Host status register (HSR), on page 6-13

Host GPIO data direction register (HDDR), on page 6-14

Host GPIO data register (HDR), on page 6-15

Host base address register (HBAR), on page 6-15

Host port control register (HPCR), on page 6-16

Both hardware and software resets disable the HI08. After a reset, the HI08 signals are

configured as GPIO and disconnected from the DSP56300 core (that is, the signals are left

floating).

6.6.1 Host Control Register (HCR)

This read/write register controls the HI08 interrupt operation. Initialization values for HCR bits

are presented in Section 6.6.9, DSP-Side Registers After Reset, on page 6-20.

9876

54321

HF3

HF2

HCIE HTIE HRIE

—Reserved bit; read as 0; write to 0 for future compatibility.

Figure 6-6. Host Control Register (HCR) (X:$FFFFC2)

Table 6-8. Host Control Register (HCR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

15–5

Reserved. Write to 0 for future compatibility.

4–3

HF[3 –2]

Host Flags 2, 3

General-purpose flags for DSP-to-host communication. The DSP core can

set or clear HF[3–2]. The values of HF[3–2] are reflected in the interface

status register (ISR); that is, if they are modified by the DSP software, the

host processor can read the modified values by reading the ISR. These two

general-purpose flags can be used individually or as encoded pairs in a

simple DSP-to-host communication protocol, implemented in both the DSP

and the host processor software. The bit value is indeterminate after an

individual reset.

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