DSP56303 datasheet(153/292 Pages) FREESCALE

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ESSI Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

7-21

9FSR

Frame Sync Relative Timing

Determines the relative timing of the receive and transmit frame sync signal

in reference to the serial data lines for word length frame sync only. When

FSR is cleared, the word length frame sync occurs together with the first bit

of the data word of the first slot. When FSR is set, the word length frame

sync occurs one serial clock cycle earlier (that is, simultaneously with the

last bit of the previous data word).

8–7

FSL[1–0]

Frame Sync Length

Selects the length of frame sync to be generated or recognized, as in

Figure 7-6 on page -23, Figure 7-9 on page -26, and Figure 7-10, Network

Mode, External Frame Sync (8 Bit, 2 Words in Frame), on page 7-26.

FSL1

FSL0

Frame Sync Length

word

bit

word

6SHFD

Shift Direction

Determines the shift direction of the transmit or receive shift register. If

SHFD is set, data is shifted in and out with the LSB first. If SHFD is cleared,

data is shifted in and out with the MSB first, as in Figure 7-12, ESSI Data

Path Programming Model (SHFD = 0), on page 7-29 and Figure 7-13 on

page -30.

5SCKD

Clock Source Direction

Selects the source of the clock signal that clocks the transmit shift register

in Asynchronous mode and both the transmit and receive shift registers in

Synchronous mode. If SCKD is set and the ESSI is in Synchronous mode,

the internal clock is the source of the clock signal used for all the transmit

shift registers and the receive shift register. If SCKD is set and the ESSI is

in Asynchronous mode, the internal clock source becomes the bit clock for

the transmit shift register and word length divider. The internal clock is

output on the SCK signal. When SCKD is cleared, the external clock source

is selected. The internal clock generator is disconnected from the SCK

signal, and an external clock source may drive this signal.

SCD2

Serial Control Direction 2

Controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an

output; when SCD2 is cleared, SC2 is an input.

Note:

Programming the ESSI to use an internal frame sync (that is,

SCD2 = 1 in CRB) causes the SC2 and SC1 signals to be

programmed as outputs. However, if the corresponding

multiplexed pins are programmed by the Port Control Register

(PCR) to be GPIOs, the GPIO Port Direction Register (PRR)

chooses their direction. The ESSI uses an external frame sync if

GPIO is selected. To assure correct operation, either program the

GPIO pins as outputs or configure the pins in the PCR as ESSI

signals. The default selection for these signals after reset is GPIO.

This note applies to both ESSI0 and ESSI1.

Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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