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DSP56303 数据表(PDF) 156 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 156 Page - Freescale Semiconductor, Inc |
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156 / 292 page  DSP56303 User’s Manual, Rev. 2 7-24 Freescale Semiconductor Enhanced Synchronous Serial Interface (ESSI) Figure 7-7. CRB SYN Bit Operation External Frame SYNC SC1 Asynchronous (SYN = 0) Transmitter Clock Frame SYNC Receiver Clock Frame SYNC SR STD SC2 External Transmit Frame External Receive Frame Internal Frame SYNC SC0 SCK External Transmit Clock External Receive Clock Internal Clock ESSI Bit Clock NOTE: Transmitter and receiver may have different clocks and frame syncs. SYNCHRONOUS (SYN = 1) Transmitter Clock Frame SYNC Receiver Clock Frame SYNC SRD ST SC2 Internal Frame SYNC SCK External Clock Internal Clock ESSI Bit Clock NOTE: Transmitter and receiver may have the same clock frame syncs. |
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