DSP56303 datasheet(165/292 Pages) FREESCALE

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GPIO Signals and Registers

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

7-33

RSMA and RSMB (as in Figure 7-12 and Figure 7-13) can be seen as one 32-bit register, RSM.

Bit n in RSM (RSn) is an enable/disable control bit for time slot number N. When RSn is cleared,

all the data signals of the enabled receivers are tri-stated during time slot number N. Data

transfers from the receive data register(s) to the receive shift register(s), but the RDF and ROE

flags are not set. Consequently, during a disabled slot, no receiver full interrupt is generated. The

DSP is interrupted only for enabled slots. When RSn is set, the receive sequence proceeds

normally. Data is received during slot number N, and the RDF flag is set.

When the bits in the RSMx are set, the frame being transmitted is unaffected, but the next frame

transmission is affected. If the RSMx is read, it shows the current setting. When the internal data

bus reads RSMA or RSMB, the register contents occupy the two low-order bytes of the data bus,

and the high-order byte is filled by 0.

After a hardware RESET signal or a software RESET instruction, the RSM register is reset to

$FFFFFFFF, enabling all 32 time slots for data transmission.

7.6 GPIO Signals and Registers

The functionality of each ESSI port is controlled by three registers: port control register (PCRC,

PCRD), port direction register (PRRC, PRRD), and port data register (PDRC, PDRD).

7.6.1 Port Control Registers (PCRC and PCRD)

The read/write 24-bit PCRs control the functionality of the signal lines for ESSI0 and ESSI1.

Each of the PCR bits 5–0 controls the functionality of the corresponding signal line. When a

PCR[i] bit is set, the corresponding port signal is configured as an ESSI signal. When a PCR[i]

bit is cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware

RESET

signal or a software RESET instruction clears all PCR bits.

RS31

RS30

RS29

RS28

9876

5432

RS27

RS26

RS25

RS24

RS23

RS22

RS21

RS20

RS19

RS18

RS17

RS16

–Reserved. Read as zero. Write with zero for future compatibility.

(ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1)

Figure 7-17. ESSI Receive Slot Mask Register B (RSMB)

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