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DSP56303 数据表(PDF) 166 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 166 Page - Freescale Semiconductor, Inc |
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166 / 292 page ![]() DSP56303 User’s Manual, Rev. 2 7-34 Freescale Semiconductor Enhanced Synchronous Serial Interface (ESSI) 7.6.2 Port Direction Registers (PRRC and PRRD) The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO signals when they are enabled by the associated Port Control Register (PCRC or PCRD, respectively). When PRRC[i] or PRRD[i] is set, the corresponding signal is an output (GPO) signal. When PRRC[i] or PRRD[i] is cleared, the corresponding signal is an input (GPI) signal. Either a hardware RESET signal or a software RESET instruction clears all PRRC and PRRD bits. Table 7-6 summarizes the ESSI port signal configurations. 7.6.3 Port Data Registers (PDRC and PDRD) Bits 5–0 of the read/write PDRs write data to or read data from the associated ESSI GPIO signal lines if they are configured as GPIO signals. If a port signal PC[i] or PD[i] is configured as an input (GPI), the corresponding PDRC[i] pr PDRD[i] bit reflects the value present on the input 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7654 3210 PCx5 PCx4 PCx3 PCx2 PCx1 PCx0 Note: For Px[5–0], a 0 selects Pxn as the signal and a 1 selects the specified ESSI signal. For ESSI0, the GPIO signals are PC[5–0] and the ESSI signals are STD0, SRD0, SCK0, and SC0[2–0]. For ESSI1, the GPIO signals are PD[5–0] and the ESSI signals are STD1, SRD1, SCK1, and SC1[2–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 7-18. Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 76 54 32 10 PRx5 PRx4 PRx3 PRx2 PRx1 PRx0 Note: For bits 5–0, a 0 configures PRxn as a GPI and a 1 configures PRxn as a GPO. For ESSI0, the GPIO signals are PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding direction bits for Port C GPIOs are PRC[5–0]. The corresponding direction bits for Port D GPIOs are PRD[5–0]. = Reserved. Read as zero. Write with zero for future compatibility. Figure 7-19. Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE) Table 7-6. ESSI Port Signal Configurations PCRC/PCRD[i] PRRC/PRRD[i] Port Signal[i] Function 1 X ESSI0/ESSI1 0 0 Port C/Port D GPI 0 1 Port C/Port D GPO X: The signal setting is irrelevant to the Port Signal[i] function. |
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