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TMS320F2811 数据表(PDF) 132 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 132 Page - Texas Instruments |
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132 / 173 page  Electrical Specifications 131 April 2001 − Revised July 2007 SPRS174O 6.27 External Interface Ready-on-Read Timing With One External Wait State Table 6−33. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) PARAMETER MIN MAX UNIT td(XCOH-XZCSL) Delay time, XCLKOUT high to zone chip-select active low 1 ns td(XCOHL-XZCSH) Delay time, XCLKOUT high/low to zone chip-select inactive high −2 3 ns td(XCOH-XA) Delay time, XCLKOUT high to address valid 2 ns td(XCOHL-XRDL) Delay time, XCLKOUT high/low to XRD active low 1 ns td(XCOHL-XRDH Delay time, XCLKOUT high/low to XRD inactive high −2 1 ns th(XA)XZCSH Hold time, address valid after zone chip-select inactive high † ns th(XA)XRD Hold time, address valid after XRD inactive high † ns † During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles. Table 6−34. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) MIN MAX UNIT ta(A) Access time, read data from address valid (LR + AR) − 14‡ ns ta(XRD) Access time, read data valid from XRD active low AR − 12‡ ns tsu(XD)XRD Setup time, read data valid before XRD strobe inactive high 12 ns th(XD)XRD Hold time, read data valid after XRD inactive high 0 ns ‡ LR = Lead period, read access. AR = Active period, read access. See Table 6−28. Table 6−35. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)§ MIN MAX UNIT tsu(XRDYsynchL)XCOHL Setup time, XREADY (synchronous) low before XCLKOUT high/low 15 ns th(XRDYsynchL) Hold time, XREADY (synchronous) low 12 ns te(XRDYsynchH) Earliest time XREADY (synchronous) can go high before the sampling XCLKOUT edge 3 ns tsu(XRDYsynchH)XCOHL Setup time, XREADY (synchronous) high before XCLKOUT high/low 15 ns th(XRDYsynchH)XZCSH Hold time, XREADY (synchronous) held high after zone chip select high 0 ns § The first XREADY (synchronous) sample occurs with respect to E in Figure 6−33: E = (XRDLEAD + XRDACTIVE) tc(XTIM) When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to be low, it will be sampled again each tc(XTIM) until it is found to be high. For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth. Table 6−36. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)¶ MIN MAX UNIT tsu(XRDYAsynchL)XCOHL Setup time, XREADY (asynchronous) low before XCLKOUT high/low 11 ns th(XRDYAsynchL) Hold time, XREADY (asynchronous) low 8 ns te(XRDYAsynchH) Earliest time XREADY (asynchronous) can go high before the sampling XCLKOUT edge 3 ns tsu(XRDYAsynchH)XCOHL Setup time, XREADY (asynchronous) high before XCLKOUT high/low 11 ns th(XRDYasynchH)XZCSH Hold time, XREADY (asynchronous) held high after zone chip select high 0 ns ¶ The first XREADY (asynchronous) sample occurs with respect to E in Figure 6−34: E = (XRDLEAD + XRDACTIVE −2) tc(XTIM) When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found to be low, it will be sampled again each tc(XTIM) until it is found to be high. For each sample, setup time from the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE −3 +n) tc(XTIM) − tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth. |
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