TMS320F2811 datasheet(133/173 Pages) TI

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Electrical Specifications

132

April 2001 − Revised July 2007

SPRS174O

Lead

Active

Trail

DIN

td(XCOH-XZCSL)

td(XCOH-XA)

td(XCOHL-XRDL)

td(XCOHL-XZCSH)

td(XCOHL-XRDH)

WS (Synch)

XCLKOUT=XTIMCLK

XCLKOUT=1/2 XTIMCLK

XZCS0AND1, XZCS2,

XZCS6AND7

XA[0:18]

XRD

XWE

XR/W

XD[0:15]

XREADY(Synch)

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an

alignment cycle before an access to meet this requirement.

B. During alignment cycles, all signals will transition to their inactive state.

C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes

alignment cycles.

D. For each sample, setup time from the beginning of the access (D) can be calculated as:

D = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL

E. Reference for the first sample is with respect to this point

E = (XRDLEAD + XRDACTIVE) tc(XTIM)

where n is the sample number: n = 1, 2, 3, and so forth.

th(XRDYsynchL)

tsu(XRDYsynchL)XCOHL

tsu(XD)XRD

ta(XRD)

ta(A)

th(XD)XRD

th(XRDYsynchH)XZCSH

= Don’t care. Signal can be high or low during this time.

Legend:

tsu(XRDHsynchH)XCOHL

See Note D

See Note E

te(XRDYsynchH)

See Note D

See Notes A and B

See Note C

Figure 6−33. Example Read With Synchronous XREADY Access

XTIMING register parameters used for this example:

XRDLEAD

XRDACTIVE

XRDTRAIL

USEREADY

X2TIMING

XWRLEAD

XWRACTIVE

XWRTRAIL

READYMODE

≥1

N/A†

0 = XREADY

(Synch)

† N/A = “Don’t care” for this example

TMS320F2811 数据表(PDF) 133 Page - Texas Instruments

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