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TMS320F2811 数据表(PDF) 137 Page - Texas Instruments

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部件名 TMS320F2811
功能描述  Digital Signal Processors
PDF  173 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320F2811 数据表(HTML) 137 Page - Texas Instruments

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Electrical Specifications
136
April 2001 − Revised July 2007
SPRS174O
Lead 1
Active
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XA[0:18]
XD[0:15]
td(XCOHL-XWEH)
td(XCOHL-XZCSH)
td(XCOH-XA)
WS (Async)
XZCS0AND1, XZCS2,
XZCS6AND7
XRD
XWE
XR/W
td(XCOH-XZCSL)
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE −3 + n) tc(XTIM) − tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE −2) tc(XTIM)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
th(XD)XWEH
th(XRDYasynchL)
DOUT
tdis(XD)XRNW
th(XRDYasynchH)XZCSH
See Note E
See Note D
= Don’t care. Signal can be high or low during this time.
Legend:
tsu(XRDYasynchL)XCOHL
tsu(XRDYasynchH)XCOHL
td(XWEL-XD)
td(XCOHL-XWEL)
SeeNotes
A and B
SeeNoteC
te(XRDYasynchH)
XREADY(Asynch)
Figure 6−36. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A†
N/A†
N/A†
1
0
≥1
3
≥1
1 = XREADY
(Async)
† N/A = “Don’t care” for this example



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