TMS320F2811 datasheet(140/173 Pages) TI

140 / 173 page

Electrical Specifications

139

April 2001 − Revised July 2007

SPRS174O

Table 6−41. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)†‡§

MIN

MAX

UNIT

td(HL-HiZ)

Delay time, XHOLD low to Hi-Z on all Address, Data, and Control

4tc(XTIM)+tc(XCO)

td(HL-HAL)

Delay time, XHOLD low to XHOLDA low

4tc(XTIM+2tc(XCO)

td(HH-HAH)

Delay time, XHOLD high to XHOLDA high

4tc(XTIM)

td(HH-BV)

Delay time, XHOLD high to Bus valid

6tc(XTIM)

† When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.

‡ The state of XHOLD is latched on the rising edge of XTIMCLK.

§ After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of XCLKOUT. Thus,

for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified.

XCLKOUT

(1/2 XTIMCLK)

XHOLD

XR/W,

XZCS0AND1,

XZCS2,

XZCS6AND7

XD[15:0]

Valid

XHOLDA

td(HL-HiZ)

td(HH-HAH)

High-Impedance

XA[18:0]

Valid

High-Impedance

td(HH-BV)

td(HL-HAL)

High-Impedance

See Note A

See Note B

NOTES:

A All pending XINTF accesses are completed.

B Normal XINTF operation resumes.

Figure 6−38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)

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