TMS320F2811 datasheet(144/173 Pages) TI

144 / 173 page

Electrical Specifications

143

April 2001 − Revised July 2007

SPRS174O

ADCIN0

10 pF

Ron

1 k

Ω

1.25 pF

Switch

Typical Values of the Input Circuit Components:

Switch Resistance (Ron):

1 k

Ω

Sampling Capacitor (Ch):

1.25 pF

Parasitic Capacitance (Cp): 10 pF

Source Resistance (Rs):

Ω

28x DSP

Source

Signal

Figure 6−39. ADC Analog Input Impedance Model

6.31.4

ADC Power-Up Control Bit Timing

ADC Power Up Delay

ADC Ready for Conversions

PWDNBG

PWDNREF

PWDNADC

Request for

ADC

Conversion

td(BGR)

td(PWD)

Figure 6−40. ADC Power-Up Control Bit Timing

Table 6−44. ADC Power-Up Delays†

MIN

TYP

MAX

UNIT

td(BGR)

Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 register

(ADCBGRFDN1/0) are to be set to 1 before the ADCPWDN bit is enabled.

td(PWD)

Delay time for power-down control to be stable. Bit 5 of the ADCTRL3 register

µs

td(PWD)

Delay time for power-down control to be stable. Bit 5 of the ADCTRL3 register

(ADCPWDN) is to be set to 1 before any ADC conversions are initiated.

† These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions

are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at the same time.

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