ST10F280 datasheet(149/186 Pages) STMICROELECTRONICS

149 / 186 page

ST10F280

149/186

19.2 - System Configuration Registers

The ST10F280 has registers used for different configuration of the overall system. These registers are

described below.

SYSCON (FF12h / 89h)

SFR

Reset Value: 0xx0h

Notes: 1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence.

2. Register SYSCON cannot be changed after execution of the EINIT instruction.

15 14 13

STKSZ

ROMS1 SGTDIS ROMEN BYTDIS

CLKEN WRCFG CSCFG

PWD

CFG

OWD

DIS

BDR

STEN

XPEN VISIBLE

XPER-

RW1

XPER-SHARE

XBUS Peripheral Share Mode Control

‘0’: External accesses to XBUS peripherals are disabled

‘1’: XBUS peripherals are accessible via the external bus during hold mode

VISIBLE

Visible Mode Control

‘0’: Accesses to XBUS peripherals are done internally

‘1’: XBUS peripheral accesses are made visible on the external pins

XPEN

XBUS Peripheral Enable bit

‘0’: Accesses to the on-chip X-Peripherals and XRAM are disabled

‘1’: The on-chip X-Peripherals are enabled.

BDRSTEN

Bidirectional Reset Enable

‘0’: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this pin)

‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.

OWDDIS

Oscillator Watchdog Disable Control

‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If

there is no activity on XTAL1 for at least 1

µs, the CPU clock is switched automatically to PLL’s

base frequency (2 to 10MHz).

‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The

PLL is turned off to reduce power supply current.

PWDCFG

Power Down Mode Configuration Control

‘0’: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low,

otherwise the instruction has no effect. Exit power down only with reset.

‘1’: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast

external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting

one enabled EXxIN pin or with external reset.

CSCFG

Chip Select Configuration Control

‘0’: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE

‘1’: Unlatched Chip Select lines: CSx change with rising edge of ALE.

WRCFG

Write Configuration Control (Inverted copy of bit WRC of RP0H)

‘0’: Pins WR and BHE retain their normal function

‘1’: Pin WR acts as WRL, pin BHE acts as WRH.

CLKEN

System Clock Output Enable (CLKOUT)

‘0’: CLKOUT disabled: pin may be used for general purpose I/O

‘1’: CLKOUT enabled: pin outputs the system clock signal.

ST10F280 数据表(PDF) 149 Page - STMicroelectronics

ST10F280 数据表(HTML) 149 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载