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ST10F280 数据表(PDF) 150 Page - STMicroelectronics

部件名 ST10F280
功能描述  16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM
PDF  186 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F280 数据表(HTML) 150 Page - STMicroelectronics

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Table 37 : Stack Size Selection
BUSCON0 (FF0Ch / 86h)
SFR
Reset Value: 0xx0h
BUSCON1 (FF14h / 8Ah)
SFR
Reset Value: 0000h
BUSCON2 (FF16h / 8Bh)
SFR
Reset Value: 0000h
BUSCON3 (FF18h / 8Ch)
SFR
Reset Value: 0000h
BYTDIS
Disable/Enable Control for Pin BHE (Set according to data bus width)
‘0’: Pin BHE enabled
‘1’: Pin BHE disabled, pin may be used for general purpose I/O.
ROMEN
Internal Memory Enable (Set according to pin EA during reset)
‘0’: Internal Memory disabled: accesses to the Memory area use the external bus
‘1’: Internal Memory enabled.
SGTDIS
Segmentation Disable/Enable Control
‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)
‘1’: Segmentation disabled (Only IP is saved/restored).
ROMS1
Internal Flash Memory Mapping
‘0’: Internal Flash Memory area mapped to segment 0 (00’0000H...00’7FFFH)
‘1’: Internal Flash Memory area mapped to segment 1 (01’0000H...01’7FFFH).
STKSZ
System Stack Size
Selects the size of the system stack (in the internal RAM) from 32 to 1024 words.
<STKSZ>
Stack Size
(Words)
Internal RAM Addresses (Words) of Physical Stack
Significant Bits of
Stack Pointer SP
0 0 0 b
256
00’FBFEh...00’FA00h (Default after Reset)
SP.8...SP.0
0 0 1 b
128
00’FBFEh...00’FB00h
SP.7...SP.0
0 1 0 b
64
00’FBFEh...00’FB80h
SP.6...SP.0
0 1 1 b
32
00’FBFEh...00’FBC0h
SP.5...SP.0
1 0 0 b
512
00’FBFEh...00’F800h (not for 1K Byte IRAM)
SP.9...SP.0
1 0 1 b
-
Reserved. Do not use this combination
-
1 1 0 b
-
Reserved. Do not use this combination
-
1 1 1 b
1024
00’FDFEh...00’FX00h (Note: No circular stack)
00’FX00h represents the lower IRAM limit, i.e.
1K Byte: 00’FA00h, 2K Byte: 00’F600h, 3K Byte: 00’F200h
SP.11...SP.0
15
14
13
12
11
10
9
876
5
4
3210
CSWEN0
CSREN0 RDYPOL0 RDYEN0
-
BUS ACT0 ALE CTL0
-
BTYP
MTTC0 RWDC0
MCTC
RW
RW
RW
RW
RW2
RW2
RW1
RW
RW
RW
15
14
13
12
11
10
9
8
76
5
4
3210
CSWEN1
CSREN1 RDYPOL1 RDYEN1
-
BUSACT1
ALECTL1
-
BTYP
MTTC1 RWDC1
MCTC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
15
14
13
12
11
10
9
8
76
5
4
3210
CSWEN2
CSREN2 RDYPOL2 RDYEN2
-
BUSACT2
ALECTL2
-
BTYP
MTTC2 RWDC2
MCTC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
15
14
13
12
11
10
9
8
76
5
4
3210
CSWEN3
CSREN3 RDYPOL3 RDYEN3
-
BUSACT3
ALECTL3
-
BTYP
MTTC3 RWDC3
MCTC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW



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