M32CSLASH8B datasheet(110/406 Pages) RENESAS

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Under development

M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 93 of 385

9.6

System Clock Protect Function

The system clock protect function prohibits the clock setting from being rewritten in order to prevent the CPU

clock source from being changed when a program goes out of control.

When the PM21 bit in the PM2 register is set to 1 (disables a clock change), the following bits cannot be written:

• Bits CM02, CM05, and CM07 in the CM0 register

• Bits CM10 and CM17 in the CM1 register

• The CM20 bit in the CM2 register

• All bits in the PLC0 register

The CPU clock continues running when the WAIT instruction is executed.

Figure 9.19 shows a procedure to use the system clock protect function. Follow the procedure while the CM05 bit

in the CM0 register is set to 0 (main clock oscillates) and the CM07 bit to 0 (main clock as CPU clock source).

Figure 9.19

Procedure to Use System Clock Protect Function

Start

PM2 register: PM21 bit = 1

(Note 1)

PRCR register: PRC1 bit = 0

End

PRCR register: PRC1 bit = 1

Enable writing to registers associated with clocks

NOTE:

1. When entering wait mode, execute the WAIT instruction while the PM21 bit in the PM2 register is set to 0.

Disable a clock change

Disable writing to registers associated with clocks

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