M32CSLASH8B datasheet(119/406 Pages) RENESAS

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M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 102 of 385

11.6

Interrupt Request Acknowledgement

Software interrupts occur when their corresponding instructions are executed. The INTO instruction, however,

requires the O flag in the FLG register to be 1. Special interrupts occur when their corresponding interrupt requests

are generated.

For the peripheral function interrupts to be acknowledged, the following conditions must be met:

• I flag = 1

• IR bit = 1

• Bits ILVL2 to ILVL0 > IPL

The I flag, IPL, IR bit, and bits ILVL2 to ILVL0 are independent of each other. The I flag and IPL are in the FLG

11.6.1

I Flag and IPL

The I flag enables and disables maskable interrupts. When the I flag is set to 1 (enable), all maskable interrupts

are enabled; when the I flag is set to 0 (disable), they are disabled. The I flag automatically becomes 0 after

reset.

IPL is 3 bits wide and indicates the Interrupt Priority Level (IPL) from level 0 to level 7. If a requested interrupt

has higher priority level than IPL, the interrupt is acknowledged.

Table 11.4 lists interrupt priority levels associated with IPL.

Table 11.4

Interrupt Priority Levels

11.6.2

Interrupt Control Registers and RLVL Register

The Interrupt Control Registers are used to control the peripheral function interrupts. Figures 11.4 and 11.5

show the Interrupt Control Registers. Figure 11.6 shows the RLVL register.

IPL2 to IPL0

Required Interrupt Priority Levels to Be Acknowledged

for Maskable Interrupts

Level 1 and above

Level 2 and above

Level 3 and above

Level 4 and above

Level 5 and above

Level 6 and above

Level 7 and above

All maskable interrupts are disabled

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