M32CSLASH8B datasheet(120/406 Pages) RENESAS

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Under development

M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 103 of 385

Figure 11.4

Interrupt Control Register (1/2)

b7 b6 b5 b4

Interrupt Control Register

Symbol

TA0IC to TA4IC

TB0IC to TB5IC

S0TIC to S4TIC

S0RIC to S4RIC

BCN0IC to BCN4IC

DM0IC to DM3IC

AD0IC

KUPIC

Address

006Ch, 008Ch, 006Eh, 008Eh, 0070h

0094h, 0076h, 0096h, 0078h, 0098h, 0069h

0090h, 0092h, 0089h, 008Bh, 008Dh

0072h, 0074h, 006Bh, 006Dh, 006Fh

0071h, 0091h, 008Fh, 0071h(1), 0091h(2)

0068h, 0088h, 006Ah, 008Ah

0073h

0093h

Bit Symbol

Bit Name

ILVL0

After Reset

XXXX X000b

NOTES:

1. The BCN0IC register shares the address with the BCN3IC register.

2. The BCN1IC register shares the address with the BCN4IC register.

3. The IR bit can be set to 0 only. Do not set to 1.

Function

Interrupt priority level select bits

ILVL1

ILVL2

b2 b1 b0

0 0 0: Level 0 (interrupt disabled)

0 0 1: Level 1

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

−

(b7-b4)

−

Interrupt request bit(3)

0: Interrupt not requested

1: Interrupt requested

Unimplemented.

Write 0. Read as undefined value.

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