M32CSLASH8B datasheet(121/406 Pages) RENESAS

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M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 104 of 385

Figure 11.5

Interrupt Control Register (2/2)

11.6.2.1

Bits ILVL2 to ILVL0

Bits ILVL2 to ILVL0 determine an interrupt priority level. The higher the interrupt priority level is, the higher

priority the interrupt has.

When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is enabled

only when its interrupt priority level is higher than IPL. When bits ILVL2 to ILVL0 are set to 000b (level 0), the

interrupt is disabled.

11.6.2.2

IR Bit

The IR bit is automatically set to 1 (interrupt requested) by hardware when an interrupt request is generated.

After an interrupt request is acknowledged and an interrupt sequence in the corresponding interrupt vector is

executed, the IR bit is automatically set to 0 (interrupt not requested) by hardware.

The IR bit can be set to 0 by a program. Do not set it to 1.

b7 b6 b5 b4

Symbol

INT0IC to INT2IC

INT3IC to INT5IC(1)

Address

009Eh, 007Eh, 009Ch

007Ch, 009Ah, 007Ah

After Reset

XX00 X000b

Function

Bit Symbol

Bit Name

Interrupt Control Register

ILVL0

Interrupt priority level

select bits

ILVL1

ILVL2

b2 b1 b0

0 0 0: Level 0 (interrupt disabled)

0 0 1: Level 1

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

POL

LVS

Interrupt request bit(2)

Polarity switch bit(3)

Level sensitive/

edge sensitive switch bit(4)

0 : Edge sensitive

1 : Level sensitive

0: Interrupt not requested

1: Interrupt requested

0: Falling edge / "L" level selected

1: Rising edge / "H" level selected

−

(b7-b6)

−

Unimplemented.

Write 0. Read as undefined value.

NOTES:

1. When a 16-bit data bus is used in microprocessor mode and memory expansion mode, pins INT3 to INT5 are used as data bus.

In this case, set bits ILVL2 to ILVL0 in registers INT3IC to INT5IC to 000b.

2. The IR bit can be set to 0 only. Do not set to 1.

3. Set the POL bit to 0 when its corresponding bit in the IFSR register is set to 1 (both edges).

4. When the LVS bit is set to 1, set its corresponding bit in the IFSR register to 0 (one edge).

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