M32CSLASH8B datasheet(131/406 Pages) RENESAS

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M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 114 of 385

11.8

NMI Interrupt

The NMI interrupt is non-maskable. The NMI interrupt occurs when a signal applied to the P8_5/NMI pin changes

from “H” level to “L” level. A read from the P8_5 bit in the P8 register returns the input level of the NMI pin.

When the NMI interrupt is not used, connect the NMI pin to VCC1 via a resistor (pull-up). Each “H” or “L” width

of the signal applied to the NMI pin must be 2 CPU clock cycles + 300 ns or more.

11.9

Key Input Interrupt

The IR bit in the KUPIC register becomes 1 when an falling edge is detected at any of the pins P10_4 to P10_7 set

to input mode. The key input interrupt can also be used as key-on wake-up function to exit wait mode or stop mode.

To use the key input interrupt, do not use pins P10_4 to P10_7 as A/D input. Figure 11.13 shows a block diagram of

the key input interrupt. When an “L” signal is applied to one of the pins P10_4 to P10_7 in input mode, a falling

edge detected at the other pins is not recognized as an interrupt request signal.

When the PSC_7 bit in the PSC register is set to 1 (AN_4 to AN_7), the input buffer for the port and the key input

interrupt is disconnected. Therefore, the pin level cannot be obtained by reading the Port P10 register in input

mode. Also, the IR bit in the KUPIC register does not become 1 even if a falling edge is detected at pins KI0 to

KI3.

Figure 11.13

Key Input Interrupt Block Diagram

Key input interrupt request

P10_7/KI3

PU31 bit

PD10_7 bit

Pull-up

transistor

Pull-up

transistor

Pull-up

transistor

Pull-up

transistor

PD10_7 bit

PD10_6 bit

PD10_5 bit

PD10_4 bit

P10_6/KI2

P10_5/KI1

P10_4/KI0

PSC_7 bit

PD10_4 to PD10_7: Bits in the PD10 register

PSC_7: Bit in the PSC register

PU31: Bit in the PUR3 register

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