M32CSLASH8B datasheet(133/406 Pages) RENESAS

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M32C/8B Group

12. Watchdog Timer

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 116 of 385

12. Watchdog Timer

The watchdog timer is used to detect the program running improperly. The watchdog timer contains a 15-bit free-

running counter. If a write to the WDTS register is not performed due to a program running out of control, the free-

running counter underflows, which results in the watchdog timer interrupt generation or the MCU reset. When

operating the watchdog timer, write to the WDTS register in a shorter cycle than the watchdog timer cycle in such as

the main routine.

Tables 12.1 and 12.2 list specifications of the watchdog timer. Figure 12.1 shows a block diagram of the watchdog

timer. Figures 12.2 and 12.3 show registers associated with the watchdog timer.

Table 12.1

Watchdog Timer Specifications (1/2)

NOTE:

1. The watchdog timer shares the same vector with the oscillation stop detection interrupt and voltage monitor

interrupt.

Table 12.2

Watchdog Timer Specifications (2/2)

fCPU: CPU clock frequency

fROC: On-chip oscillator clock frequency

NOTES:

1. Once the PM22 bit is set to 1, it cannot be set to 0 by a program.

2. Difference between the calculation result and actual period can be one count source cycle of the counter.

3. A write to the CM10 bit in the CM1 register is disabled. Writing a 1 has no effect and the MCU does not enter

stop mode. The watchdog timer interrupt cannot be used to exit wait mode.

Item

Specification

Count operation

The free-running counter decrements

Count start condition

Writing to the WDTS register:

A write to the WDTS register initializes a free-running counter and the counter

decrements from 7FFFh

When underflows

One of the following occurs (selectable using the CM06 bit in the CM0 register):

• Watchdog timer interrupt generation(1)

• MCU reset

After underflows

The counter continues decrementing

(when the watchdog timer interrupt is selected)

Read from watchdog timer

A read from bit 4 to bit 0 in the WDC register returns bit 14 to bit 10 of the free-running

counter

Item

Bit Setting and Specification

PM22 bit in PM2 register(1)

001

CM07 bit in CM0 register

0 or 1

WDC7 bit in WDC register

0 or 1

Clock source

CPU clock

On-chip oscillator

Clock divided by MCD register

Sub clock

Prescaler

Divide-by-16

Divide-by-128

Divide-by-2

not available

Count source for counter

× 16

× 128

× 2

Time-out period (formula)(2)

× 524288

× 4194304

× 65536

× 32768

Time-out period (reference)

Approx. 16.4 ms

fCPU = 32 MHz

Approx. 131.1 ms

fCPU = 32 MHz

Approx. 2 s

fCPU = 32 kHz

Approx. 32.8 ms

fROC = 1 MHz

Operation in wait mode,

stop mode, and hold state

Stops

Operates(3)

fCPU

fROC

fCPU

fROC

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