H8SSLASH2214 datasheet(520/936 Pages) RENESAS

520 / 936 page

Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 460 of 872

REJ09B0189-0400

12.2.3

Transmit Shift Register (TSR)

—

Bit

R/W

TSR is a register used to transmit serial data.

To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then

sends the data to the TxD pin starting with the LSB (bit 0).

When transmission of one byte is completed, the next transmit data is transferred from TDR to

TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not

performed if the TDRE bit in SSR is set to 1.

TSR cannot be directly read or written to by the CPU.

12.2.4

Transmit Data Register (TDR)

R/W

Bit

Initial value

R/W

TDR is an 8-bit register that stores data for serial transmission.

When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and

starts serial transmission. Continuous serial transmission can be carried out by writing the next

transmit data to TDR during serial transmission of the data in TSR.

TDR can be read or written to by the CPU at all times.

TDR is initialized to H'FF by a reset, in standby mode, watch mode, subactive mode, and subsleep

mode or module stop mode.

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