H8SSLASH2214 datasheet(522/936 Pages) RENESAS

522 / 936 page

Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 462 of 872

REJ09B0189-0400

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is

performed in transmission, and parity bit checking in reception. In clocked synchronous mode

with a multiprocessor format, parity bit addition and checking is not performed, regardless of the

PE bit setting.

Bit 5

Description

Parity bit addition and checking disabled

(Initial value)

Parity bit addition and checking enabled*

Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/

E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity

(even or odd) specified by the O/

E bit.

Bit 4—Parity Mode (O/

E): Selects either even or odd parity for use in parity addition and

checking.

The O/

E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and

checking, in asynchronous mode. The O/

E bit setting is invalid in clocked synchronous mode,

when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor

format is used.

Bit 4

Description

Even parity*

(Initial value)

Odd parity*

Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

2. When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.

The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the

STOP bit setting is invalid since stop bits are not added.

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