H8SSLASH2214 datasheet(521/936 Pages) RENESAS

521 / 936 page

Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 461 of 872

REJ09B0189-0400

12.2.5

Serial Mode Register (SMR)

R/W

CHR

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

R/W

SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate

generator clock source.

SMR can be read or written to by the CPU at all times.

SMR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in

module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.

Bit 7—Communication Mode (C/

A): Selects asynchronous mode or clocked synchronous mode

as the SCI operating mode.

Bit 7

Description

Asynchronous mode

(Initial value)

Clocked synchronous mode

Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In

clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.

Bit 6

CHR

Description

8-bit data

(Initial value)

7-bit data*

Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not

possible to choose between LSB-first or MSB-first transfer.

H8S/2214 数据表(PDF) 521 Page - Renesas Technology Corp

H8S/2214 数据表(HTML) 521 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载