H8SSLASH2214 datasheet(153/936 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 93 of 872

REJ09B0189-0400

5.1.3

Pin Configuration

Table 5.1 summarizes the pins of the interrupt controller.

Table 5.1

Interrupt Controller Pins

Name

Symbol

I/O

Function

Nonmaskable interrupt

NMI

Input

Nonmaskable external interrupt; rising or

falling edge can be selected

External interrupt

requests 7 to 0

IRQ7 to IRQ0 Input

Maskable external interrupts; rising, falling, or

both edges, or level sensing, can be selected

External expansion

interrupt sources 7 to 0

EXIRQ7 to

EXIRQ0

Input

Interrupts from external expansion modules.

Interrupt is accepted on low level.

5.1.4

Table 5.2 summarizes the registers of the interrupt controller.

Table 5.2

Interrupt Controller Registers

Name

Abbreviation

R/W

Initial Value

Address*

System control register

SYSCR

R/W

H'01

H'FDE5

IRQ sense control register H

ISCRH

R/W

H'00

H'FE12

IRQ sense control register L

ISCRL

R/W

H'00

H'FE13

IRQ enable register

IER

R/W

H'00

H'FE14

IRQ status register

ISR

R/(W)*

H'00

H'FE15

Interrupt priority register A

IPRA

R/W

H'77

H'FEC0

Interrupt priority register B

IPRB

R/W

H'77

H'FEC1

Interrupt priority register C

IPRC

R/W

H'77

H'FEC2

Interrupt priority register D

IPRD

R/W

H'77

H'FEC3

Interrupt priority register F

IPRF

R/W

H'77

H'FEC5

Interrupt priority register G

IPRG

R/W

H'77

H'FEC6

Interrupt priority register J

IPRJ

R/W

H'77

H'FEC9

Interrupt priority register K

IPRK

R/W

H'77

H'FECA

Interrupt priority register M

IPRM

R/W

H'77

H'FECC

Notes: 1. Lower 16 bits of the address.

2. Can only be written with 0 for flag clearing.

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