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H8S/2214 数据表(PDF) 160 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 160 Page - Renesas Technology Corp |
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160 / 936 page  Section 5 Interrupt Controller Rev.4.00 Sep. 18, 2008 Page 100 of 872 REJ09B0189-0400 IRQn interrupt request IRQnE IRQnF S R Q Clear signal Edge/level detection circuit IRQnSCA, IRQnSCB IRQn input Note: n = 7 to 0 Figure 5.2 Block Diagram of Interrupts IRQn Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Note: n = 7 to 0 Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. Since interrupt request flags IRQ7F to IRQ0F are set when the setting condition is satisfied, regardless of the IER setting, only the necessary flags should be referenced. (3) EXIRQ7 to EXIRQ0 Interrupts Interrupts EXIRQ7 to EXIRQ0 are for use by external expansion modules. An interrupt is requested by a low-level input signal at one of pins EXIRQ7 to EXIRQ0. |
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