H8SSLASH2214 datasheet(161/936 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 101 of 872

REJ09B0189-0400

5.3.2

Internal Interrupts

There are 31 sources for internal interrupts from on-chip supporting modules.

• For each on-chip supporting module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1

for a particular interrupt source, an interrupt request is issued to the interrupt controller.

• The interrupt priority level can be set by means of IPR.

• The DMAC and DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request.

When the DMAC and DTC is activated by an interrupt, the interrupt control mode and

interrupt mask bits are not affected.

5.3.3

Interrupt Exception Handling Vector Table

Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority.

Priorities among modules can be set by means of the IPR. The situation when two or more

modules are set to the same priority, and priorities within a module, are fixed as shown in

table 5.4.

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