H8SSLASH2214 datasheet(163/936 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 103 of 872

REJ09B0189-0400

Vector

Address*

Interrupt Source

Origin of

Interrupt

Source

Vector

Number

Advanced

Mode

IPR

Priority

TGI1A (TGR1A input

capture/compare match)

TGI1B (TGR1B input

capture/compare match)

TCI1V (overflow 1)

TCI1U (underflow 1)

TPU

channel 1

H'00A0

H'00A4

H'00A8

H'00AC

IPRF2 to

IPRF 0

High

TGI2A (TGR2A input

capture/compare match)

TGI2B (TGR2B input

capture/compare match)

TCI2V (overflow 2)

TCI2U (underflow 2)

TPU

channel 2

H'00B0

H'00B4

H'00B8

H'00BC

IPRG6 to

IPRG 4

DEND0A (channel 0/channel 0A

transfer end)

DEND0B (channel 0B transfer end)

DEND1A (channel 1/channel 1A

transfer end)

DEND1B (channel 1B transfer end)

DMAC

H'0120

H'0124

H'0128

H'012C

IPRJ6 to

IPRJ4

ERI0 (receive error 0)

RXI0 (reception completed 0)

TXI0 (transmit data empty 0)

TEI0 (transmission end 0)

SCI

channel 0

H'0140

H'0144

H'0148

H'014C

IPRJ2 to

IPRJ 0

ERI1 (receive error 1)

RXI1 (reception completed 1)

TXI1 (transmit data empty 1)

TEI1 (transmission end 1)

SCI

channel 1

H'0150

H'0154

H'0158

H'015C

IPRK6 to

IPRK 4

ERI2 (receive error 2)

RXI2 (reception completed 2)

TXI2 (transmit data empty 2)

TEI2 (transmission end 2)

SCI

channel 2

H'0160

H'0164

H'0168

H'016C

IPRK2 to

IPRK 0

EXIRQ0

EXIRQ1

EXIRQ2

EXIRQ3

External

module

104

105

106

107

H'01A0

H'01A4

H'01A8

H'01AC

IPRM6 to

IPRM4

EXIRQ4

EXIRQ5

EXIRQ6

EXIRQ7

108

109

110

111

H'01B0

H'01B4

H'01B8

H'01DC

IPRM2 to

IPRM0

Low

Note: * Lower 16 bits of the start address.

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