H8SSLASH2214 datasheet(192/936 Pages) RENESAS

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Section 6 Bus Controller

Rev.4.00 Sep. 18, 2008 Page 132 of 872

REJ09B0189-0400

6.2.6

Pin Function Control Register (PFCR)

—

R/W

—

R/W

—

R/W

—

R/W

AE3

R/W

AE0

R/W

AE2

R/W

AE1

R/W

Bit

Modes 4 and 5

Initial value

Modes 6 and 7

Initial value

R/W

PFCR is an 8-bit readable/writable register that performs address output control in external

expanded mode.

PFCR is initialized to H'0D (modes 4 and 5) or H'00 (modes 6 and 7) by a power-on reset and in

hardware standby mode. It retains its previous state in a manual reset and in software standby

mode.

Bits 7 to 4—Reserved: Only 0 should be written to these bits.

Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or

disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When

a pin is enabled for address output, the address is output regardless of the corresponding DDR

setting. When a pin is disabled for address output, it becomes an output port when the

corresponding DDR bit is set to 1.

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