H8SSLASH2214 datasheet(193/936 Pages) RENESAS

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Section 6 Bus Controller

Rev.4.00 Sep. 18, 2008 Page 133 of 872

REJ09B0189-0400

Bit 3

Bit 2

Bit 1

Bit 0

AE3

AE2

AE1

AE0

Description

A8 to A23 output disabled

(Initial value*1)

A8 output enabled; A9 to A23 output disabled

A8, A9 output enabled; A10 to A23 output disabled

A8 to A10 output enabled; A11 to A23 output disabled

A8 to A11 output enabled; A12 to A23 output disabled

A8 to A12 output enabled; A13 to A23 output disabled

A8 to A13 output enabled; A14 to A23 output disabled

A8 to A14 output enabled; A15 to A23 output disabled

A8 to A15 output enabled; A16 to A23 output disabled

A8 to A16 output enabled; A17 to A23 output disabled

A8 to A17 output enabled; A18 to A23 output disabled

A8 to A18 output enabled; A19 to A23 output disabled

A8 to A19 output enabled; A20 to A23 output disabled

A8 to A20 output enabled; A21 to A23 output disabled

(Initial value*2)

A8 to A21 output enabled; A22, A23 output disabled

A8 to A23 output enabled

Notes: 1. In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.

In expanded mode with ROM, address pins A0 to A7 are made address outputs by

setting the corresponding DDR bits to 1.

2. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.

In ROMless expanded mode, address pins A0 to A7 are always made address output.

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