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PC87309VLJ 数据表(PDF) 175 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 175 Page - National Semiconductor (TI) |
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175 / 192 page ![]() Device Specifications 175 www.national.com 10.3.5 Transmitter Timing Notes: 1. Not tested. Guaranteed by design. 1. See write cycle timing in Section 10.3.3 on page 172. 2. See read cycle timing in Section 10.3.3 on page 172. Symbol Parameter Min Max Unit tHR Delay from WR (WR THR) to Reset IRQ 40 nsec tIR Delay from RD (RD IIR) to Reset IRQ (THRE) 55 nsec tIRS Delay from Initial IRQ Reset to Transmit Start1 8 24 Baud Output Cycles tSI Delay from Initial Write to IRQ1 16 24 Baud Output Cycles tSTI Delay from Start Bit to IRQ (THRE)1 8 Baud Output Cycles START DATA (5-8) PARITY STOP (1-2) START tIRS tSTI tHR tSI tHR tIR Serial Out (SOUT) Interrupt (THRE) WR (WR THR) Note 1 RD (RD IIR) Note 2 |
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