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PC87309VLJ 数据表(PDF) 176 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 176 Page - National Semiconductor (TI) |
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176 / 192 page ![]() Device Specifications 176 www.national.com 10.3.6 Receiver Timing Standard Mode 1. This is internal timing and is therefore not tested. 2. Not tested. Guaranteed by design. Symbol Parameter Min Max Unit tRAI1 Delay from Active Edge of RD to Reset IRQ 78 nsec tRAI2 Delay from Active Edge of RD to Reset IRQ 78 nsec tRAI3 Delay from Active Edge of RD to Reset IRQ 78 nsec tRINT Delay from Inactive Edge of RD (RD LSR) to Reset IRQ 55 nsec tSCD Delay from RCLK to Sample Time1 41 nsec tSINT Delay from Stop bit to Set Interrupt2 2 Baud Output Cycles RCLK Sample CLK RDR LSI RD (RD RBR) RD (RD LSR) Interrupt Interrupt tSINT tRINT tRAI1 tSCD 8 CLKS ACTIVE ACTIVE SIN DATA (5-8) STOP Sample Clock |
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