ST7LITE49K2 datasheet(110/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

110/245

11.3.3

Functional description

Timebase counter 1

The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it

starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the

counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two

counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the

LTCSR1 register.

When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is

generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1

Input capture

The 8-bit Input Capture register is used to latch the free-running upcounter (Counter 1) 1

after a rising or falling edge is detected on the LTIC pin. When an Input Capture occurs, the

ICF bit is set and the LTICR register contains the counter 1 value. An interrupt is generated

if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.

The LTICR is a read-only register and always contains the data from the last Input Capture.

Input Capture is inhibited if the ICF bit is set.

Timebase counter 2

Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR

stored in the LTARR register. A counter overflow event occurs when the counter rolls over

from FFh to the LTARR reload value. Software can write a new value at any time in the

LTARR register, this value will be automatically loaded in the counter when the next overflow

occurs.

When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an

interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software

reading the LTCSR2 register.

Figure 54.

Input capture timing diagram

04h

8-bit COUNTER 1

01h

fOSC/32

xxh

02h

03h

05h

06h

07h

04h

LTIC PIN

ICF FLAG

LTICR REGISTER

CLEARED

4µs

(@ 8 MHz fOSC)

fCPU

BY S/W

07h

READING

LTIC REGISTER

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