ST7LITE49K2 datasheet(113/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

113/245

Bit 6 = ICF Input capture flag

This bit is set by hardware and cleared by software by reading the LTICR register.

Writing to this bit does not change the bit value.

0: No Input Capture

1: An Input Capture has occurred

Note:

After an MCU reset, software must initialize the ICF bit by reading the LTICR register

Bit 5 = TB Timebase period selection bit

This bit is set and cleared by software.

0: Timebase period = tOSC * 8000 (1 ms @ 8 MHz)

1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz)

Bit 4 = TB1IE Timebase Interrupt enable bit

This bit is set and cleared by software.

0: Timebase (TB1) interrupt disabled

1: Timebase (TB1) interrupt enabled

Bit 3 = TB1F Timebase Interrupt flag

This bit is set by hardware and cleared by software reading the LTCSR register. Writing

to this bit has no effect.

0: No counter overflow

1: A counter overflow has occurred

Bits 2:0 = Reserved, must be kept cleared.

Lite timer input capture register (LTICR)

Reset value: 0000 0000 (00h)

Bits 7:0 = ICR[7:0] Input Capture value

These bits are read by software and cleared by hardware after a reset. If the ICF bit in the

LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling

edge occurs on the LTIC pin.

ICR7

ICR6

ICR5

ICR4

ICR3

ICR2

ICR1

ICR0

Read only

Table 41.

Lite timer register mapping and reset values

Address

(Hex.)

label

765

43210

LTCSR2

Reset Value

000

TB2IE

TB2F

LTARR

Reset Value

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

LTCNTR

Reset Value

CNT7

CNT6

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

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