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ST7LITE49K2 数据表(PDF) 117 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 117 Page - STMicroelectronics |
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117 / 245 page  ST7LITE49K2 On-chip peripherals 117/245 Figure 55. Timer block diagram 1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 18: ST7LITE49K2 interrupt mapping) Output compare register 1 Output compare circuit Overflow detect circuit 1/2 1/4 1/8 8-bit buffer Internal bus LATCH1 OCMP1 ICAP1 EXTCLK fCPU Timer interrupt ICF2 ICF1 TIMD 0 0 OCF2 OCF1 TOF PWM OC1E EXEDG IEDG2 CC0 CC1 OC2E OPM FOLV2 ICIE OLVL1 IEDG1 OLVL2 FOLV1 OCIE TOIE LATCH2 8 low 16 8 high 16 16 16 16 CR1 (control register 1) CR 2 (control register 2) CSR (control/status register ) 6 16 8 high EXEDG Timer internal bus Input capture register 1 CC[1:0] Counter pin pin pin register (1) 16-bit timer peripheral interface 8 Low 8 high 8 Low 8 high 8 Low 8 high 8 Low Output compare register 2 Input capture register 2 Alternate counter register Edge detect circuit 2 Edge detect circuit 1 ICAP2 pin OCMP2 pin |
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