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ST7LITE49K2 数据表(PDF) 119 Page - STMicroelectronics |
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ST7LITE49K2 数据表(HTML) 119 Page - STMicroelectronics |
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119 / 245 page  ST7LITE49K2 On-chip peripherals 119/245 A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 57. Counter timing diagram, internal clock divided by 2 Figure 58. Counter timing diagram, internal clock divided by 4 Figure 59. Counter timing diagram, internal clock divided by 8 Note: The device is in reset state when the internal reset signal is high, when it is low the device is running. CPU clock FFFD FFFE FFFF 0000 0001 0002 0003 Internal reset Timer clock Counter register Timer overflow flag (TOF) FFFC FFFD 0000 0001 CPU clock Internal reset Timer clock Counter register Timer overflow flag (TOF) CPU clock Internal reset Timer clock Counter register Timer overflow flag (TOF) FFFC FFFD 0000 |
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