LSM6DST datasheet(107/180 Pages) STMICROELECTRONICS

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LSM6DST

180

9.58

I3C_BUS_AVB (62h)

I3C_BUS_AVB register (r/w)

Table 161. I3C_BUS_AVB register description

9.59

INTERNAL_FREQ_FINE (63h)

Internal frequency register (r)

Table 163. INTERNAL_FREQ_FINE register description

Table 160. I3C_BUS_AVB register

0(1)

1. This bit must be set to '0' for the correct operation of the device.

IBI_RST_

ACK

0(1)

I3C_Bus_

Avb_Sel1

I3C_Bus_

Avb_Sel0

0(1)

PD_DIS_

INT1

IBI_RST_ACK

When this bit is set to '1', IBI is reset with master acknowledge.

When this bit is set to '0', IBI is reset when the interrupt is served (reading output

data or the interrupt source registers).

I3C_Bus_Avb_

Sel[1:0]

These bits are used to select the bus available time when I3C IBI is used.

Default value: 00

(00: bus available time equal to 50 μsec (default);

01: bus available time equal to 2 μsec;

10: bus available time equal to 1 msec;

11: bus available time equal to 25 msec)

PD_DIS_INT1

This bit allows disabling the INT1 pull-down.

(0: Pull-down on INT1 enabled (pull-down is effectively connected only when no

interrupts are routed to the INT1 pin or when I3C dynamic address is assigned);

1: Pull-down on INT1 disabled (pull-down not connected)

Table 162. INTERNAL_FREQ_FINE register

FREQ_

FINE7

FREQ_

FINE6

FREQ_

FINE5

FREQ_

FINE4

FREQ_

FINE3

FREQ_

FINE2

FREQ_

FINE1

FREQ_

FINE0

FREQ_FINE[7:0]

Difference in percentage of the effective ODR (and Timestamp Rate) with

respect to the typical. Step: 0.15%. 8-bit format, 2's complement.

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