LSM6DST datasheet(108/180 Pages) STMICROELECTRONICS

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LSM6DST

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UI_INT_OIS (6Fh)

OIS interrupt configuration register and accelerometer self-test enable setting. The primary

interface can write this register when the OIS_CTRL_FROM_UI bit in the

FUNC_CFG_ACCESS (01h) register is equal to 1 (Primary IF Full control mode); this

mode) and shows the content of the SPI2_INT_OIS (6Fh) register.

Table 165. UI_INT_OIS register description

Table 164. UI_INT_OIS register

INT2_

DRDY_OIS

LVL2_OIS

DEN_LH_

OIS

0(1)

1. This bit must be set to '0' for the correct operation of the device.

SPI2_

READ_EN

0(1)

INT2_DRDY_

OIS

Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2

settings.

LVL2_OIS

Enables level-sensitive latched mode on the OIS chain. Default value: 0

DEN_LH_

OIS

Indicates polarity of DEN signal on OIS chain

(0: DEN pin is active-low; 1: DEN pin is active-high)

SPI2_

READ_EN

In Primary IF full control mode, enables Auxiliary SPI for reading OIS data in registers

SPI2_OUTX_L_G_OIS (22h) and SPI2_OUTX_H_G_OIS (23h) through

SPI2_OUTZ_L_A_OIS (2Ch) and SPI2_OUTZ_H_A_OIS (2Dh). Default value: 0

(0: OIS data reading from Auxiliary SPI disabled;

1: OIS data reading from Auxiliary SPI enabled)

LSM6DST 数据表(PDF) 108 Page - STMicroelectronics

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