IA188EM-PQF100I-R datasheet(21/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

active state at reset with a memory range of 64 Kbytes (F0000h to FFFFFh), external ready required, and

three wait states automatically inserted. The upper end of the memory range always ends at FFFFFh,

whereas the lower end of this upper memory range is programmable.

The value of the UMCS register is F03Bh at reset.

5 4 3

LB2 – LB0

1 1 1 R2 R1-R0

Reserved [15] (bit 15) – Set to 1.

LB [2:0] (bits 14–12) – Lower Boundary. These bits determine the bottom of the memory accessed

by the ucs_n chip selects.

UMCS Block Size Programming Values

Memory

Block

Size

Starting

Address

LB2 – LB0

Comments

64K

F0000h

111b

Default

128K

E0000h

110b

256K

C0000h

100b

512K

80000h

000b

Reserved (bits 11 – 8)

DA (bit 7) – Disable Address. When set to 0, the address is driven onto the address bus (ad15 – ad0)

during the address phase of a bus cycle when ucs_n is asserted. If DA is set to 1, the address bus is

disabled, and the address is not driven on the address bus when ucs_n is asserted, providing some

measure of power saving. This bit is set to 0 at reset.

If bhe_n/aden_n is held at 0 during the rising edge of res_n, then the address bus is always driven

independent of the setting of DA.

Reserved (bit 6) – Set to 0.

Reserved (bit 5 – 3) – Set to 1.

R2 (bit 2) Ready Mode – When this bit is set to 0, an external ready is required. But when set to 1, the

external ready is ignored. In either case, however, the value of the R1 - R0 bits determine the number

of wait states inserted.

R [1:0] (bits 1-0) - Wait-State Value. The number of wait states inserted into an access to the lcs_n

memory area is determined by the value of these bits. This number ranges from 0 to 3 (R1 – R0 = 00b

to 11b).

SPBAUD (088h) - Serial Port BAUD Rate Divisor Register.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

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