IA188EM-PQF100I-R datasheet(60/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

The three most significant bits of the address bus (a19 – a17) start with their normal function on power-

on reset, permitting the processor to begin fetching instructions from the boot address FFFF0h.

Furthermore, normal function is the default setting for dt/r_n, den_n, and srdy on power-on reset.

s6/clkdiv2_n and uzi_n automatically return to normal operation in the event that the ad15-ad0 bus

override is enabled. The ad15-ad0 bus override is enabled if the bhe_n/aden_n for the IA186EM, or the

rfsh2_n/aden_n for the IA188EM, is held low during power-on reset.

Pin Descriptions

a19 (pio9), a18 (pio8), a17 (pio7), a16 – a0 Address Bus (synchronous outputs with tristate)

These pins are the system’s source of non-multiplexed I/O or memory addresses and occur a half

CLKOUTA cycle before the multiplexed address/data bus (ad15-ad0 for the IA186EM or ao15_ao8 and

ad7-ad0 for the AI188EM). The address bus is tristated during a bus hold or reset.

ad15 – ad8 IA186EM Address/Data bus (level-sensitive synchronous inouts with tristate)

These pins are the system’s source of time-multiplexed I/O or memory addresses and data. The address

function of these pins can be disabled. (See bhe_n/aden_n pin description.) If the address function of

these pins is enabled, the address will be present on this bus during t1 of the bus cycle and data will be

present during t2, t3, and t4 of the same bus cycle.

If whb_n is not active, these pins are tristated during t2, t3, and t4 of the bus cycle.

The address/data bus is tristated during a bus hold or reset.

These pins can be used to load the internal Reset Configuration register (RESCON, offset 0F6h) with

configuration data during a power-on reset.

ad7 – ad0 Address/Data bus (level-sensitive synchronous inouts with tristate)

These pins are the system’s source of time-multiplexed low-order byte of the addresses for I/O or memory

and 8-bit data. The low-order address byte will be present on this bus during t1 of the bus cycle and the 8-

bit data will be present during t2, t3, and t4 of the same bus cycle.

The address function of these pins can be disabled. (See bhe_n/aden_n pin description.)

If wlb_n is not active, these pins are tristated during t2, t3, and t4 of the bus cycle. The address/data bus is

tristated during a bus hold or reset.

ao15 – ao8 IA188EM Address-only bus (level-sensitive synchronous outputs with tristate)

The address-only bus will contain valid high-order address bits during the bus cycle (t1, t2, t3, and t4) if the

bus is enabled.

These pins are combined with ad7-ad0 to complete the multiplexed address bus and are tristated during a

bus hold or reset condition.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

IA188EM-PQF100I-R 数据表(PDF) 60 Page - InnovASIC, Inc

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