IA188EM-PQF100I-R datasheet(62/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

Holding aden_n low during power-on reset, both the address and data are driven onto the ad bus

independently of the DA bit setting. This pin is normally sampled one clock cycle after the rising edge of

res_n.

clkouta – Clock Output A (synchronous output)

This pin is the internal clock output to the system. Bits 9, 8, and 2-0 of the Power-Save Control register

(PDCON) control the output of this pin, which may be tristated, output the crystal input frequency (X1),

or output the power save frequency (internal processor frequency after divisor). clkouta can be used as a

full speed clock source in power-save mode. The A.C. timing specifications that are clock-related refer to

clkouta, which remains active during reset and hold conditions.

clkoutb – Clock Output B (synchronous output)

This pin is an additional clock out put to the system. Bits 11, 10, and 2-0 of the Power-Save Control

may output the power save frequency (internal processor frequency after divisor). clkoutb remains active

during reset and hold conditions.

den_n (pio5) – Data Enable Strobe ( synchronous output with tristate)

This pin provides an output enable to an external bus data bus transmitter or receiver. This signal is

asserted during I/O, memory, and interrupt acknowledge processes and is deasserted when dt/r_n

undergoes a change of state. It is tristated for a bus hold or reset.

drq1-drq (pio12-pio13) – DMA Requests (synchronous level-sensitive inputs)

drq0 – An external device that is ready for DMA channel 1 or 0 to carry out a transfer indicates to the

microcontroller this readiness on these pins. They are level triggered, internally synchronized, not

latched, and must remain asserted until dealt with.

dt/r_n (pio4) – Data Transmit or Receive (synchronous output with tristate)

The microntroller transmits data when dt/r_n is pulled high and receives data when this pin is pulled low.

It floats during a reset or bus hold condition.

gnd – Ground

Six or seven pins, depending on package, connect the microcontroller to the system ground.

hlda – Bus Hold Acknowledge (synchronous output)

This pin is pulled high to signal the system that the microntroller has ceded control of the local bus, in

response to a high on the hold signal by an external bus master, after the microcontroller has completed

the current bus cycle. The assertion of hlda is accompanied by the tristating of den_n, rd_n, wr_n,

s2_n-s0_n, ad15-ad0, s6, a19-a0, bhe_n, whb_n, wlb_n, and dt/r_n, followed by the driving high of the

chip selects ucs_n, lcs_n, mcs3_n - mcs0_n, pcs6_n – pcs5_n, and pcs3_n – pcs0_n. The external bus

master releases control of the local bus by the deassertion of hold that in turn induces the microcontroller

to deassert the hlda. The microcontroller can take control of the bus if necessary (to execute a refresh for

example), by deasserting hlda without the bus master first deasserting hold. This requires that the

external bus master be able to deassert hold to permit the microcontroller to access the bus.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

IA188EM-PQF100I-R 数据表(PDF) 62 Page - InnovASIC, Inc

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