IA188EM-PQF100I-R datasheet(32/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

CONT (bit 0) – Continuous Mode Bit. The timer will run continuously when this bit is set to 1. The

timer will stop after each count run and EN will be cleared if this bit is set to 0.

T2COMPA (062h), - Timer Maxcount COMpare Registers.

T1COMPB (05ch)

T1COMPA (05ah)

T0COMPB (054h)

T0COMPA (052h)

These registers contain the maximum count value that is compared to the respective count register. Timer

0 and Timer 1 have two of these compare registers each.

If Timer 0 or Timer 1 or both are configured to count and compare firstly to register A and then register

B, the tmrout0 or tmrout1 signals may be used to generate various duty-cycle wave forms.

Timer 2 has only one compare register, T2COMPA.

If one of these timer maxcount compare registers is set to 0000h, the respective timer will count from

0000h to FFFFh before generating an interrupt request. For example, a timer configured in this manner

with a 40MHz clock will interrupt every 6.5536 mS.

The value of these registers is undefined at reset.

TC15 – TC0

TC [15:0] (bits 15-0) – Timer Compare Value. The timer will count to the value in the respective

T2CNT (060h) - Timer CouNT Registers.

T1CNT (058h)

T0CNT (050h),

These registers are incremented by one every four internal clock cycles if the relevant timer is enabled.

The Increment of Timer 0 and Timer 1 may also be controlled by external signals tmrin0 and tmrin1

respectively, or prescaled by Timer 2.

Comparisons are made between the count registers and maxcount registers and action taken dependent on

achieving the maximum count.

The value of these registers is undefined at reset.

TC15 – TC0

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IA188EM-PQF100I-R 数据表(PDF) 32 Page - InnovASIC, Inc