IA188EM-PQF100I-R datasheet(49/133 Pages) INNOVASIC

49 / 133 page

IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

Clock and Power Management

A phase-lock-loop (PLL) and a second programmable system clock output (CLKOUTB) are included in

the clock and power management unit. The internal clock is the same frequency as the crystal but with a

duty cycle of 45% - 55 %, as a worse case, generated by the PLL obviating the need for an x2 external

clock. A power-on reset (POR) resets the PLL.

Figure 2. Crystal Configuration

System Clocks

If required, the internal oscillator can be driven by an external clock source that should be connected to

X1, leaving X2 unconnected.

The clock outputs clkouta and clkoutb may be enabled or disabled individually (Power-Save Control

and the other to run at the power-save frequency.

Figure 3. Organization of Clock

Crystal

Am186/188EM

Recommended range of

values for C1 and C2 are:

C1 = 15pF +/- 20%

C2 = 22pF +/- 20%

PLL

Power-Save

Divisor

(/2 to /128)

Mux

Processor Internal Clock

Time

Delay

6 +/- 2.5nS

Drive enable

X1,

clkouta

clkoutb

IA188EM-PQF100I-R 数据表(PDF) 49 Page - InnovASIC, Inc

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