IA188EM-PQF100I-R datasheet(24/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

Reserved (bits 15-7) – Reserved – Set to 0.

TEMT (bit 6) – Transmitter Empty. When both the transmit shift register and the transmit register are

empty, this bit is set indicating to software that it is safe to disable the transmitter.

This bit is read-only.

THRE (bit 5) – Transmit Holding Register Empty. When this bit is 1, the corresponding transmit

holding register is ready to accept data. This is a read-only bit.

RDR (bit 4) – Receive Data Ready. When this bit is 1, the respective SPRD register contains valid

data. This is a read/write bit and can be reset only by reading the corresponding Receive register.

BRKI (bit 3) –Break Interrupt. This bit indicates that a break has been received when this bit is set to

1 and causes a serial port interrupt request.

NOTE: This bit should be reset by software.

FER (bit 2) – Framing Error Detected. When the receiver samples the rxd line as low when a stop bit

is expected (line high) a framing error is generated setting this bit.

NOTE: This bit should be reset by software.

PER (bit 1) - Parity Error Detected. When a parity error is detected in either mode 1 or 3, this bit is

set.

NOTE: This bit should be reset by software.

OER (bit 0) – Overrun Error Detected. When new data overwrites valid data in the receive register

(because it hasn’t been read) an overrun error is detected setting this bit.

NOTE: This bit should be reset by software.

SPCT (080h) - Serial Port ConTrol Register.

This register controls both transmit and receive parts of the serial port.

The value of the SPCT register is 0000h at reset.

15 14 13 12

Reserved

LOOP

BRK

VAL

PMODE

WLGN

STP

TMODE

RSIE

RMODE

Reserved (bits 15-12) – Reserved. Set to 0.

TXIE (bit 11) – Transmitter Ready Interrupt Enable. This bit enables the generation of an interrupt

requests whenever the transmit holding register is empty (THRE bit 1). The respective port does not

generate interrupts when this bit is 0. Interrupts continue to be generated as long as THRE and the

TXIE are 1.

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