IA188EM-PQF100I-R datasheet(55/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

Interrupt Table Notes

If the user does not change priority levels, the default priority level will be used for the interrupt sources.

1. Instruction execution generates interrupts.

2. Performed in the same manner as for the 8086 & 8088.

3. An ESC opcode causes a trap.

4. Only one IRQ is generated for the three timers so they share priority level with regard to other

sources. The timers themselves have an interrupt priority order among themselves (2A > 2B > 2C).

5. These interrupt types are programmable in Slave mode.

6. Not available in slave mode.

Timer Control

The IA186EM and IA188EM each have three 16-bit programmable timers.

Timer0 and timer1 each have an input and an output connected to external pins that permit them to count

or time events, produce variable duty-cycle waveforms or non-repetitive waveforms. Timer1 can also be

configured as a Watchdog timer.

Timer2 does not have any external connections. Therefore, it is confined to internal functions such as

real-time coding, time-delay applications, a prescaler for timer0 and timer1, or to synchronize DMA

transfers.

The Peripheral Control Block contains eleven 16-bit registers to control the programmable timers. The

present value of the timer is located in the associated timer-count register, which may be read from or

written to at any time regardless of whether the timer is in operation or not. The value of the timer-count

The maximum value that each timer can reach is determined by the value stored in the associated

maximum count register. Upon reaching this maximum count value, the timer count register is reset to 0

in the same clock cycle that this count was attained, so that the timer count register does not store this

maximum value. Both timer0 and timer1 have two maximum count registers, a primary and a secondary

Timer0 and timer1 can have the maximum count registers configured in one of two ways, primary only or

both primary and secondary. If only the primary is configured to operate, on reaching the maximum

count the output pin will go low for one clock period. If both the primary and secondary registers are

enabled, the output pin reflects the state of whichever of the two registers is in control at the time,

generating the required waveform that is dependent on the two values in the maximum count registers.

The timers can operate at a quarter of the internal clock frequency, as they are polled every fourth clock

period. Alternatively, an external clock can be used. However, in this case the timer output can take six

clock cycles to respond to the input.

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