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IA188EM-PQF100I-R 数据表(PDF) 92 Page - InnovASIC, Inc |
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IA188EM-PQF100I-R 数据表(HTML) 92 Page - InnovASIC, Inc |
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92 / 133 page  IA186EM/IA188EM Data Sheet 8/16-BIT Microcontrollers As of Production Version -03 No. Name Description MIN MAX Units 34 tWHDX Data Hold after wr_n tCLCL ns 35 tWHDEX wr_n Inactive to den_n Inactive tCLCH ns 41 tDSHLH ds_n Inactive to ale Inactive tCLCH ns 59 tRHDX rd_n High to Data Hold on ad Bus 0 ns 65 tAVWL a Address Valid to wr_n Low tCLCL + tCHCL ns 66 tAVRL a Address Valid to rd_n Low tCLCL + tCHCL ns 67 tCHCSV clkoutA High to lcs_n/usc_n Valid 0 9 ns 68 tCHAV clkoutA High to a Address Valid 0 8 ns 87 tAVBL a Address Valid to whb_n/wlb_n Low tCHCL - 1.5 tCHCL ns Refresh Timing Cycle Parameters 79 tCHRFD clkoutA High to rfsh_n Valid 0 12 ns 82 tCLRF clkoutA High to rfsh_n Invalid 0 12 ns 85 tRFCY rfsh_n Cycle Time 6tCLCL ns 86 tLCRF lcs_n Inactive to rfsh_n Active Delay 2tCLCL ns clkin Timing 36 tCKIN X1 Period 25 66 ns 37 tCLCK X1 Low Time 7.5 ns 38 tCHCK X1 High Time 7.5 ns 39 tCKHL X1 Fall Time 5 ns 40 tCKLH X1 Rise time 5 ns clkout Timing 42 tCLCL clkoutA Period 25 ns 43 tCLCH clkoutA Low Time TCLCL/2 ns 44 tCHCL clkoutA High Time TCLCL/2 ns 45 tCH1CH2 clkoutA Rise Time 3 ns 46 tCL2CL1 clkoutA Fall Time 3 ns 61 tLOCK Maximum PLL Lock Time 0.5 ms 69 tCICOA X1 to clkoutA Skew 25 ns 70 tCICOB X1 to clkoutB Skew 35 ns Ready & Peripheral Timing Requirements 47 tSRYCL srdy Transition Setup Time 10 ns 48 tCLSRY srdy Transistion Hold Time 3 ns 49 tARYCH ardy Resolution Transition Setup Time 9 ns 50 tCLARX ardy Active Hold Time 4 ns 51 tARYCHL ardy Inactive Holding Time 6 ns 52 tARYLCL ardy Setup Time 9 ns 53 tINVCH Peripheral Setup Time 10 ns 54 tINVCL drq Setup Time 10 ns 3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com |
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