IA188EM-PQF100I-R datasheet(52/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

Upper Memory Chip Select

The ucs_n chip-select is for the top of memory. On reset, the micro controller begins fetching and

executing instructions at memory location FFFF0h. As a result, upper memory is usually utilized for

instruction memory. To this end, ucs_n is active on reset and has a memory range of 64Kbytes (F0000h

to FFFFFh) as default along with external ready required and three wait-states automatically inserted.

The lower boundary of ucs_n is programmable to provide ranges of 64Kbytes to 512Kbytes.

Low Memory Chip Select

The lcs_n chip-select is for lower memory. As the interrupt vector table is at the bottom of memory

beginning at 00000h, this pin us usually utilized for control data memory. Unlike ucs_n, this pin is

inactive on reset, but it can be activated by any read or write to the LMCS register.

Midrange Memory Chip Selects

There are four midrange chip-selects, mcs3_n-mcs0_n, which may be used in a user-located memory

block. The base address of the memory block may be located anywhere in the 1-Mbyte memory address

space with some exceptions. The memory spaces used by the ucs_n and lcs_n chip-selects are excluded,

as are the pcs6_n, pcs5_n, and pcs3_n – pcs0_n. If the pcs_n chip-selects are mapped to I/O space then

the MCS address range can overlap the PCS address range.

Both the Midrange Memory Chip Select (MMCS) register and the MCS and PCS Auxiliary register

(MPCS) registers are used to program the four midrange chip-selects. The MPCS register is used to

configure the block size, whereas the MMCS register configures the base address, the ready condition,

and the wait states of the memory block accessed by the mcs_n pin. The chip selects (mcs3_n-mcs0_n)

are activated by performing a read or write operation of the MMCS and MPCS registers. The assertion of

the MCS outputs occurs with the same timing as the multiplexed AD address bus (ad15-ad0 or ao15-ao8

and ad7-ad0). The a19-a0 may be used for address selection, but the timing will be delayed by a half

clock cycle over the timing used for the ucs_n and lcs_n.

Peripheral Chip Selects

There are six peripheral chip-selects, pcs6_n, pcs5_n, and pcs3_n – pcs0_n, that may be used within a

user-defined memory or I/O block. The base address of this user-defined memory block can be located

anywhere within the 1-Mbyte memory address space except for the spaces associated with the ucs_n,

lcs_n, and mcs_n chip selects. Or it may be programmed to the 64Kbyte I/O space. pcs4_n is not

available.

Both the Peripheral Chip Select (PACS) register and the MCS and PCS Auxiliary register (MPCS)

registers are used to program the six peripheral chip-selects, pcs6_n, pcs5_n, and pcs3_n – pcs0_n. The

PACS register sets the base address, the ready condition, and the wait states for the pcs3_n – pcs0_n

outputs.

The MPCS register configures pcs6_n and pcs5_n pins as either chip selects or address pins a1 and a2

respectively. When these pins are chip selects the MPCS register also configures them as being active

during memory or I/O bus cycles, and their ready and wait states.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

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