IA188EM-PQF100I-R datasheet(64/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

int3/inta1_n/irq – Maskable Interrupt Request 3 (asynchronous input) / Interrupt Acknowledge 1

(synchronous output) / Interrupt Acknowledge (synchronous output)

int3 - The int3 pin provides an indication that an interrupt request has occurred, and provided that int3 is

not masked, program execution will continue at the location specified by the int3 vector in the interrupt

vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be

edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to

ensure that it is recognized. When int1 is configured to be in cascade mode, int3 changes its function to

inta1_n.

inta1_n – this function indicates to the system that the microcontroller requires an interrupt type in

response to the interrupt request int1 when the microcontroller’s Interrupt Control Unit is in cascade

mode. The peripheral device that issued the interrupt must provide the interrupt type.

irq – With the Interrupt Control Unit of the microcontroller in slave mode, the signal on this pin allows

the microcontroller to output an interrupt request to the external master interrupt controller.

int4/pio30 – Maskable Interrupt Request 4 (asynchronous input)

int4 - The int4 pin provides an indication that an interrupt request has occurred, and provided that int4 is

not masked, program execution will continue at the location specified by the int4 vector in the interrupt

vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be

edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to

ensure that it is recognized.

lcs_n/once0_n – Lower Memory Chip Select (synchronous output with internal pull-up) / ONCE

Mode Request (input)

lcs_n - The lcs_n pin provides an indication that a memory access is occurring to the lower memory

block. The size of the Lower Memory Block and its base address are programmable, with the size

adjustable up to 512 Kbytes. lcs_n is held high during bus hold.

once0_n – (ONCE – ON Circuit Emulation). This pin and its companion pin once1_n define the

microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if both

are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE mode, all

pins are tristated and remain so until a subsequent reset. To prevent the microcontroller from entering

ONCE mode inadvertently, this pin has a weak pull-up that is only present during reset. Finally, this pin

is not tristated during bus hold.

mcs2_n – mcs0_n (no pio - pio15 – pio 14) – Midrange Memory Chip Selects (synchronous outputs

with internal pull-up)

mcs0_n - The mcs2_n and mcs0_n pins provide an indication that a memory access is in train to either

the second or third midrange memory block. The size of the Midrange Memory Block and its base

address are programmable. mcs2_n – mcs0_n are held high during bus hold and have weak pull-ups that

are only present during reset.

3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

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