数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

IA188EM-PQF100I-R 数据表(PDF) 38 Page - InnovASIC, Inc

部件名 IA188EM-PQF100I-R
功能描述  8/16-Bit Microcontrollers
PDF  133 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  INNOVASIC [InnovASIC, Inc]
网页  http://www.innovasic.com
标志 INNOVASIC - InnovASIC, Inc

IA188EM-PQF100I-R 数据表(HTML) 38 Page - InnovASIC, Inc

Back Button IA188EM-PQF100I-R Datasheet HTML 34Page - InnovASIC, Inc IA188EM-PQF100I-R Datasheet HTML 35Page - InnovASIC, Inc IA188EM-PQF100I-R Datasheet HTML 36Page - InnovASIC, Inc IA188EM-PQF100I-R Datasheet HTML 37Page - InnovASIC, Inc IA188EM-PQF100I-R Datasheet HTML 38Page - InnovASIC, Inc IA188EM-PQF100I-R Datasheet HTML 39Page - InnovASIC, Inc IA188EM-PQF100I-R Datasheet HTML 40Page - InnovASIC, Inc IA188EM-PQF100I-R Datasheet HTML 41Page - InnovASIC, Inc IA188EM-PQF100I-R Datasheet HTML 42Page - InnovASIC, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 38 / 133 page
background image
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
The value of these registers is 000Fh at reset.
15
14
13
12
11
10
9
8
7
6
5 4
3
2
1
0
Reserved
MSK
PR2 - PR0
Reserved (bits 15-4) – Set to 0.
MSK (bit 3) – Mask. Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The
interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a
duplicate of this bit.
PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the serial port interrupts in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
INTSTS (030h) – INTerrupt STatuS Register.
Master Mode
The Interrupt status register contains the interrupt request status of each of the three timers, Timer2,
Timer1, and Timer0.
15
14
13
12
11
10
9
8
7
6
5 4
3
2
1
0
DHLT
Reserved
TMR2 - TMR0
DHLT (bit 15) – DMA Halt. DMA activity is halted when this bit is 1. It is set to 1 automatically
when any non-maskable interrupt occurs and is cleared to 0 when an IRET instruction is executed.
Interrupt handlers and other time critical software may modify this bit directly to disable DMA
transfers. However, the DHLT bit should not be modified by software if the timer interrupts are
enabled as the function of this register as an interrupt request register for the timers would be
compromised.
Reserved (bits 14-3)
TMR [2:0] (bit 2-0) – Timer Interrupt Request. A pending interrupt request is indicated by the
respective timer, when any of these bits is 1. (N.B. the TMR bit in the REQST register is a logical OR
of these timer interrupt requests)
Slave Mode
When nonmaskable interrupts occur the interrupt status register controls DMA operation and the interrupt
request status of each of the three timers, Timer2, Timer1, and Timer0.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com